technobable

Solving Steve Ballmer's Interview Riddle with Game Theory

Wed, 07 Jan 2026 14:37:00 +0100

The quest

Imagine that one day, billionaire Steve Ballmer invites you to join his mission. Before you can sign on, he poses a challenge:

“I am thinking of an integer between 1 and 100. You must guess the number. After each guess, I will tell you if my number is higher or lower. Each guess costs you $1. You must keep playing until you get it right.” ¹

The question is: How much money should Steve expect to get from you on average?

Take a deep breath

…and ponder the implications of an adversary who wants you to lose.

A Simpler Problem

Let’s start with only 3 numbers. What is the expected number of questions?

Steve as the honest randomizer

If we assume Steve picks a number $(1, 2, \text{ or } 3)$ uniformly at random, our best strategy is to guess 2.

If correct (1/3 probability): 1 guess.
If incorrect (2/3 probability): 2 guesses (since the “higher/lower” hint reveals the remaining number).

The Expected value is:

\[E_{uniform} = 1 \cdot P(\text{1st try}) + 2 \cdot P(\text{2nd try})\] \[E_{uniform}(3) = 1 \cdot \left(\frac{1}{3}\right) + 2 \cdot \left(\frac{2}{3}\right) = \frac{5}{3} \approx 1.667\]

Steve as the tricky adversary

Steve didn’t become a billionaire by being dumb. If he knows you will always guess number 2 in first try, he will avoid picking it. Instead, he can pick 1 or 3, forcing you to always pay $2. In this scenario, your $E_v$ against his best response becomes 2.0.

For the 3-number game, the optimal strategies for both players are probabilistic (mixed strategies).

Steve’s Strategy: To maximize your cost, Steve should pick 1 and 3 with 40% probability each, and 2 only 20% of the time.
Your Strategy: To minimize your loss, you should guess 2 60% of the time, and 1 or 3 20% of the time each.

Under these optimal conditions, the game settles at a value of $1.80 per game. This is the Nash equilibrium. Neither player can improve their outcome by changing their strategy alone.

Solving with Linear Programming

We can model this zero-sum game using a payoff matrix $A$, where Steve (player 1) chooses rows $x$ and you (player 2) choose columns $y$.

The objective is to find:

\[\min_y \max_x (x^T A y) \quad \text{subject to} \quad B x = b, \quad Cy = c, \quad x,y \ge 0\]

This can be transformed into a standard Linear Programming (LP) problem: ²

\[\max (c'z) \quad \text{subject to} \quad Bx = b, \quad C'z \le A'x\]

From Game Tree to Game Graph

For a 3-number game, the strategy tree is manageable. As $n$ grows, the number of possible strategy paths in game tree blows up exponentially, making $n=100$ impossible to solve as a raw tree.

We can reduce the state space by recognizing that the game is a Directed Acyclic Graph (DAG). A strategy for guessing a range $[a, b]$ does not depend on how you narrowed it down to that range.

The resulting game graph is a “folded” game tree once the tree is converted into sequence form.²

Nodes: Represented as $(a, b)$, the remaining range. There are $O(n^2)$ such nodes.
Edges: Represented as $(a, b, m)$, where $m$ is the number you guess from strategy$(a, b)$. There are $O(n^3)$ such vertices.

Constraints are written for each node such that the sum of incoming vertices equals the sum of outgoing vertices. The sum of root strategies is 1.

Payout matrix: $A$ is constructed such that column $j$ corresponds to the index $(a,b,k)$. We have $A_{s,j} = 1$ when $s$ is the number Steve picked, provided $a \le s \le b$. When $s$ is outside the closed interval $[a,b]$, we have $A_{s,j} = 0$.

Symmetries

We can further reduce the game graph by encoding symmetries. For a game of size $n$ (indexed from $0$ to $n−1$), the value at vertex $(a,b,k)$ is identical to the value at vertex $(n−1−b,n−1−a,n−1−k)$. From Steve’s perspective, the probability of picking number x is equal to the probability of picking number $(n−1)−x$. Encoding these symmetries significantly reduces the number of variables the LP solver must handle.

Result

By feeding this graph-encoded LP into a solver, we find the exact value for $n=100$:

\[E_v(100) = \frac{296}{51} \approx 5.8039\]

Interestingly, Steve’s optimal distribution follows a specific pattern: he favors the “edges” of the search space. As noted by Bo Waggoner, the probability of Steve picking $1$ or $100$ is $\frac{2}{102}$, while the inner numbers $2$ through $99$ are picked with a probability of $\frac{1}{102}$.

The solver takes approximately 20 minutes on a modern desktop to reach this result.

Note: When Steve picks each number uniformly with probability $\frac{1}{100}$ we have

\[E_{uniform}(100) = 1 \cdot \frac{1}{100} + 2 \cdot \frac{2}{100} + 3 \cdot \frac{4}{100} + 4 \cdot \frac{8}{100} + 5 \cdot \frac{16}{100} + 6 \cdot \frac{32}{100} + 7 \cdot \frac{100-63}{100} = \frac{29}{5} = 5.8\]

Code for solver is available here: github.com/ra1u/steve-game

Automatc frequency domain analysis of digital ciruits

Sat, 15 Jul 2017 15:37:00 +0200

This post is about design and analysis of digital circuits using haskell as a language and clash as tool to generate digital circuits.

Main Idea

Frequency analysis can be preformed for digital circuits using only adders, multiplies and register. Intuitive reasoning to get response of single frequency from such circuitry as black box goes as. We insert Signal of complex numbers in circuitry and from resulting complex signal observe phase and amplitude. Registry in this setup is no more than rotation of phase or phase delay that depends on Nyquist frequency of input signal.

Analysis is not done in time, but directly in frequency domain. For one input frequency we get amplitude and phase of output. Approach works best for acyclic circuits, both linear (e.g. fir filter) and nonlinear circuits (e.g. frequency mixer). It can be used for linear cyclic circuits for example iir filter. Anaysis result can be presented as Bode or Nyquist plot. Experimental hacked up implementation is available at github.

Example of use

Clash compiler can be used to both design digital circuitry and analyze them using the great language Haskell. Both in time and frequency domain. Analysis in time domain is part of standard library that ships with distribution.

We can describe fir filter in language haskell for example as:

fir coeffs x = dotp coeffs (windowP x)
  where
    dotp as bs = sum (zipWith (*) as bs)

This description enables generating digital circuit by compiling in vhdl or verilog language and than burn this in FPGA or in ASIC.

We begin by generating fir coeficients. For example by using python library scipy. There is also haskell library dsp that can do same.

>>> from scipy import signal as s
>>> s.firwin2(101,freq=[0,0.5,0.55,1],gain=[1,1,1e-5,1e-5],nfreqs=1024).tolist()

this generates 101 fir coefficient-s with gain 1 in interval [0,0.55] and gain 1e-5 in interval [0.55,1] where interval represents Nyquist frequency. Nyquist frequency is frequency scaled from 0 to 1/2 of sampling frequency.

firCoef = -6.478374934754401e-05 :> 6.739792048055188e-05 :> 5.077367641329531e-05 :> -7.20036873194064e-05 :> -3.7245153312760294e-05 :> 7.249856664305871e-05 :> 2.2414720687380852e-05 :> -6.155684145140234e-05 :> -7.664810105984746e-06 :> 2.85804248573473e-05 :> -3.6152309490646324e-08 :> 3.86526486767599e-05 :> -1.4006284245813091e-05 :> -0.00015120836046040963 :> 7.361032727845754e-05 :> 0.0003152579566734551 :> -0.00021195524189591408 :> -0.0005277210648487832 :> 0.0004703572783638681 :> 0.0007717574734980716 :> -0.0008954627919597703 :> -0.001012627857164383 :> 0.0015349575580967327 :> 0.0011943982184525286 :> -0.002432123228258949 :> -0.0012377957439342097 :> 0.0036197818250699866 :> 0.0010392111520942885 :> -0.005114324388627113 :> -0.0004703430147278584 :> 0.00691059332253219 :> -0.0006228059544207712 :> -0.008978362677236961 :> 0.0024241985527292402 :> 0.011261032711201649 :> -0.005160469774066745 :> -0.013676935125896208 :> 0.00913292632920996 :> 0.016123357472055417 :> -0.014794308598846265 :> -0.01848307417265467 :> 0.02293937546874407 :> 0.02063285839843857 :> -0.03523405731548666 :> -0.022453185292383104 :> 0.05602454640129296 :> 0.02383815920968249 :> -0.10138553138188472 :> -0.024704631737024998 :> 0.3167115011351708 :> 0.5250045350057191 :> 0.3167115011351717 :> -0.024704631737024647 :> -0.10138553138188545 :> 0.023838159209682245 :> 0.05602454640129442 :> -0.02245318529238117 :> -0.03523405731548606 :> 0.020632858398438054 :> 0.02293937546874406 :> -0.018483074172654032 :> -0.014794308598846393 :> 0.01612335747205424 :> 0.009132926329209059 :> -0.013676935125896086 :> -0.005160469774066614 :> 0.011261032711201845 :> 0.002424198552728965 :> -0.008978362677237601 :> -0.0006228059544210945 :> 0.006910593322532333 :> -0.0004703430147276999 :> -0.005114324388627051 :> 0.0010392111520945455 :> 0.0036197818250703288 :> -0.001237795743934232 :> -0.0024321232282593064 :> 0.0011943982184523566 :> 0.0015349575580969096 :> -0.0010126278571641848 :> -0.0008954627919598041 :> 0.000771757473497906 :> 0.00047035727836372234 :> -0.0005277210648488565 :> -0.0002119552418958731 :> 0.0003152579566736044 :> 7.361032727858147e-05 :> -0.0001512083604604247 :> -1.4006284245899888e-05 :> 3.865264867673136e-05 :> -3.6152309459163916e-08 :> 2.8580424857355213e-05 :> -7.66481010600899e-06 :> -6.15568414514097e-05 :> 2.24147206873927e-05 :> 7.249856664305469e-05 :> -3.724515331277384e-05 :> -7.200368731939395e-05 :> 5.0773676413330495e-05 :> 6.739792048057118e-05 :> -6.478374934755455e-05 :> Nil

We define our circuitry as

firCircuit x = fir firCoef x

Result of calculating response of circuit firCircuit can be presented as following graph

x axis represent frequency from 0 to Nyquist frequency and y is gain in dB. More details regarding ploting is available in testing code example available at github.

Details

Analysis can be precisely performed on acyclic circuits for both linear and some nonlinear systems. By applying iterations it is possible to analyze also cyclic circuits. Only restriction is that circutry is defined by input type that is both Num and Prependable. Prepend is using polymorphic version of register called prepend.

Naive idea I started to work from is, that we push inside signal of complex numbers. Addition is addition of complex numbers and similar for multiplication. This should work fine at least for linear circuits.

Cyclic circuits can be are analyzed getting more values from output stream and waiting for result to converge. It works for analyzing iir filters.

For mixing/nonlinear circuits multiplication of spectrum is needed. Multiplying two sin functions is expressed as following identity.

sin(a) * sin(b) = 1/2 (cos(a-b) - cos(a+b))

or when dealing in single frequency we get.

sin(x + a) * sin(x + b) == 
1/2 (cos(a - b) - cos(2x + a + b)) ==
1/2 (sin(a - b + pi/2) - sin(2x + a + b + pi/2))

Multiplying two signals on same frequency one with phase a and other with phase b results in signal decomposed in DC components and other with signal having double frequency.

Haskell type that holds phases on multiple harmonics can be Map Int (Complex Double) Where Int represents harmonics and Complex Double size and phase of a signal at that harmonics frequency. In general Num class is needed for such type. That are function + - and *.

acyclic circuits

What remains for such system is phase rotation. When we delay signal using register, we need to tell register how to delay input spectrum.

If circuit is acyclic, single value wrapped in type AnalyzerAcyclic is enough for exact analysis. This represents type of input stream and is type used as input and output of circuit.

data AnalyzerAcyclic s = 
        AnalyzerAcyclic {unAnalyzerAcyclic :: (Maybe (s -> s) , s)}

First type Maybe (s -> s) is spectrum transfer function. s -> s is function for rotating input used by registerP function is wrapped in Maybe, because instances of AnalyzerAcyclic for example fromInteger and fromRational are unable to provide better than value Nothing. For example function (+) requires forwarding valid transform function as output. Second type s is input spectrum for example Map Int (Complex Double) and represents amplitudes and phases on all harmonics frequencies.

cyclic circuits

Simple example of cyclic circuit would be

integrator sig = r where 
    r = registerP 0 r + sig

registerP is polymorphic version of register called prepend from class Prepenable with origin from prevous post and lack of theoretical foundations. Some care is required to avoid bottom or infinite loop that would happen using AnalyzerAcyclic.

Current solution is that stream is used as input. In output stream we wait for values to converge. Type that works for our case is.

data Analyzer s = Analyzer {unAnalyzer :: ([Maybe (s -> s)] , Signal s)}

First value [Maybe (s -> s)] is list of spectrum transfer functions, that is function that rotates input signal when register is reached. Second type Signal s is stream of spectrum. For registryP is required to retrieve spectrum transformation in breadth-first order. Traversing to spectrum rotate function s -> s in depth first order, would halt evaluation and would reach bottom.

For this type we need to implement Ǹum instance.

Example of + is.

da + db = FreqAn (zipWith (<|>) fa fb, liftA2 (+) a b) where
         (fa,a) = unFreqAn da
         (fb,b) = unFreqAn db

That is, spectrum transfer function is generated by merging two spectrum transfer functions one from argument da and other from db input. Addition is done trough Applicative instance of underlaying input type that needs to be instance of Applicative.

What next

Experimental library and some playground code in test.hs is available at github. It is not yet clear how to make Functor and Applicative instance of Analyzer and family. Also Prependable typclass as used here and previously to describe parallel circuits seems nice and useful, but has no theoretical foundations I am aware of and for extra only law it I came up with is broken in implementation of AnalyzerAcyclic. It is not clear what kind of nonlinear circuits beside frequency mixers are possible to analyze using such approach. There is missing bunch of utility functions and overall many questions remains open.

Fell free to reach me over git or irc at irc.freenode.com. I am hanging on channels #haskell and #clash-lang under nick ralu but you can also send mails on address starting with luka and ending with name of this domain.

Isomorphism of digital circuits

Fri, 23 Dec 2016 14:37:00 +0100

Building software in haskell is frequently expressing problem in one domain and then transfer it into another. Previous post Remote fpga call was about using type system to use and define circuits in both hardware and software.

Plan for this post is to show how to define circuits (using clash in haskell) for two different and related domains. One domain are circuits using Signal a that represent periodic clock domain where value a (like Bool or Signed 5) changes at each clock edge. Frequency and polarity of clock change are not relevant, but they are same for whole circuitry. This are synchronous digital circuits where whole circuitry operates on same clock.

Other domain is about digital synchronous circuits that at each clock receives and process n values of type a. We call such domain multi data domain or MultiSignal. Type of this data stream is Signal (Vec n a) where Vec n a is homogeneous list of exactly n elements each having type a. Such signals represents for example serialized data received over high speed bus or ADC that in one clock cycle sends more than one sample acquired at higher frequency.

We are on quest to figure out how to express circuits in both Signal and MultiSignal domain.

Whole idea summary

MultiSignal n a is defined as Signal (Vec n a) as explained earlier. After providing instance of Functor and Applicative for such type new type-class Prependable is required that generalize over delay/register with instance for both Signal and Multisignal n. This few type-classes are enough to describe synchronous circuits in both domains (Signal and MultiSignal). Finally there are few examples on how to implement primitive building blocks in Multisignal n as defined with Signal in clash-prelude library. Library

Functor

Note: If you are familiar with Functors and Applicative you can skip to prependable

We will say that Signal has property of a functor. Functor f as used in haskell defines function fmap of type (a -> b) -> f a -> f b. Additionally it requires that law fmap id == id holds.

When using with Signal function fmap has type of.

fmap :: (a -> b) -> Signal a -> Signal b
-- or equivalently
fmap :: (a -> b) -> (Signal a -> Signal b)

fmap converts combinatorial circuit having type a -> b to synchronous circuit Signal a -> Signal b. For example, combinatorial function that tels if value is positive can be naively expressed as.

isPositive x = x >= 0

Type signature of isPositive is deduced automatically by compiler as (Ord a, Num a) => a -> Bool. This tels us that such circuit can be synthesized for any a that is both Ord-erable and can be compared against. a additionally needs to be Num-ber. Only those types that has property of Num can be compared against 0. Function isPositive takes value of type a and returns Boolean.

Additionally we can manually define less generic and more restrictive type signature. To define for input that is Signed 6 for example.

isPositive :: Signed 6 -> Bool

Composing combinatorial circuits with synchronous circuits requires that we change function of type Signed 6 -> Bool to function of type Signal (Signed 6) -> Signal Bool .

isPositiveSig :: Signal (Signed 6) -> Signal Bool
isPositiveSig = fmap isPositive

Functor for Signal with function fmap provide transformation from combinatorial circuit to synchronous. Functor additionally requires that law fmap id == id holds, where id is identity function implemented as id x = x. This law guarantees that Signal behaves well and one can not implement fmap using register without breaking such law. Transformation from combinatorial to synchronous circuit is trivial in hardware level. What happens is that only type signature changes, but transformed circuitry remains same.

Before going with MultiSignal let’s take a look in functor properties of Vec n. Vec n a is homogeneous list of elements with length n and type a. For example Vec 5 (Signed 6) is array of 5 elements each having type of Signed 6. Functor Vec n has function fmap with type

fmap :: (a -> b) -> Vec n a -> Vec n b

Using isPositive :: Signed 6 -> Bool and Vec 5 (Signed 6) we can make Vec 5 Bool using fmap

 isArrayPositve :: Vec 5 (Signed 6) -> Vec 5 Bool
 isArrayPositve arr = fmap isPositive arr

or also

 isArrayPositve :: Vec 5 (Signed 6) -> Vec 5 Bool 
 isArrayPositve = fmap isPositive

Fmap is function that transform function operating over single value Signed 6 -> Bool in function operating over vector Vec 5 (Signed 6) -> Vec 5 Bool. In this case fmap makes 5 instances of function isPositive in hardware to generate isArrayPositve. We trust implementor (or check source) of library that fmap for Vec n obeys law fmap id == id. That is, transforming each element of Vec n a with id is same as Vec n a applied on function id.

Functor for MultiSignal

First we define type

data MultiSignal n a = MultiSignal {unMultiSignal :: Signal (Vec n a) }

MultiSignal is similar to Vec and parametrized over 2 types. First n is type level length, because length has to be known at compile time and a is underlying type. MultiSignal on left side of = is type definition and MultiSignal on right side of = is constructor having type Signal (Vec n a) -> MultiSignal n a . To get Signal (Vec n a) from MultiSignal n a there is unMultiSignal :: MultiSignal n a -> Signal (Vec n a) available.

MultiSignal has property of being Functor. We define MultiSignal being Functor as

instance Functor (MultiSignal n) where
    fmap f s = MultiSignal ( fmap ( fmap f ) ( unMultiSignal s ) )

We first apply unMultiSignal to s so we get Signal (Vec n a) from type MultiSignal n a. There are two fmap used here. Leftmost is over Signal where rightmost fmap is over Vec . Resulting type of fmap ( fmap f ) ( unMultiSignal s ) is Signal (Vec n a) and we finally apply MultiSignal constructor to make result type MultiSignal n a.

Applicative

So far we have functor that enables converting combinatorial circuits of type a -> b to synchronous having type Signal a -> Signal b . What remains is extending such concept to converting functions having more than one arrow. For example transforming a -> b -> c -> d in Signal a -> Signal b -> Signal c -> Signal d. Additionally we need concept of delaying Signal using register or d flip flop. Applicative enables transforming from combinatorial to synchronous circuits for arbitrary number of arrows.

Applicative class requires two functions, to be defined.

class Functor f => Applicative f where
    pure :: a -> f a
    (<*>) :: f (a -> b) -> f a -> f b

For signal we need

-- For Signal
pure :: a -> Signal a

pure changes value a to Signal a. On each clock change we get same value. Example: pure True is Signal Bool having boolean True as value on each clock.

Function (<*>) can be used as either operator or function depending on parenthesis so (<*>) a b used as function is same as a <*> b when used as operator.

-- For Signal
(<*>) :: Signal (a -> b) -> Signal a -> Signal b

First argument has type Signal (a -> b). It represents a function that is changing with clock signal. For any class that is Applicative we have available functions

liftA  :: Applicative f => (a -> b) -> f a -> f b
liftA2 :: Applicative f => (a -> b -> c) -> f a -> f b -> f c
liftA3 :: Applicative f => (a -> b -> c -> d) -> f a -> f b -> f c -> f d

Using liftAx with Signal enables converting combinatorial circuits having x inputs in synchronous circuits. For f being Signal function liftA2 becomes

liftA2 ::  (a -> b -> c) -> Signal a -> Signal b -> Signal c

liftA2 can be implemented as

liftA2 f s1 s2 = (pure f) <*> s1 <*> s2

Intermediate types are

f                      :: a -> b -> c
pure f                 :: Signal (a -> b -> c)
(pure f) <*> s1        :: Signal (b -> c)
(pure f) <*> s1 <*> s2 :: Signal c

Signal (a -> b -> c) is same as Signal (a -> (b -> c)) and this is why (pure f) <*> s1 has type Signal (b -> c)

Using this pattern liftA5 is expressed

liftA5 f s1 s2 s3 s4 s5 = (pure f) <*> s1 <*> s2 <*> s3 <*> s4 <*> s5

Function liftAx transform combinatorial circuit having arbitrary number of arrows in synchronous circuit. In hardware level such transformation is trivial and what happens is that just type of function change to make compiler happy.

Vec n is also an Applicative and works similar compared to Signal. For Vec n liftA2 when used with Vec has type.

liftA2 :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c

liftA2 for Vec n works in way that takes values at same index to produce value at same index in resulting vector using passed function. As with Functor there are Applicative functor laws that should hold for every implementation of Applicative.

Applicative functor instance of Signal and Vec are similar to reason about. Both works in way, that each value at some place represent value as a result of other values at that place. For example

liftA2 (+) (1:>2:>3:>Nil) (3:>5:>7:>Nil) == (4:>7:>10:>Nil)

MultiSignal as applicative functor

Implementing instance of Applicative functor for MultiSignal enables all required tools for transforming combinatorial circuits in domain of MultiSignal. For example liftA2 is defined in terms of Applicative for MultiSignal as

liftA2 :: (a->b->c) -> MultiSignal n a -> MultiSignal n b -> MultiSignal n c

We need to define two functions

pure :: a -> MultiSignal n a
(<*>) :: MultiSignal n (a -> b) -> MultiSignal n a -> MultiSignal n a

Implementation for Applicative

instance KnownNat n => Applicative (MultiSignal n) where
   pure x = MultiSignal (pure (pure x))
   f <*> s = MultiSignal  (fmap (<*>) fu <*> su) where
      fu = unMultiSignal f
      su = unMultiSignal s

Prependable

Prependable is typeclass to generalize over register . We would like to use single function that can be used to define delay for both Signal and MultiSignal. Prependable works as something that prepends element to the stream.

class Prependable f where
    prepend :: a -> f a -> f a

Defining prepend for Signal is just register.

instance Prependable Signal where
    prepend = register

for MultiSignal: value from register we shift to vector. What pop out at shift we store in register.

instance (KnownNat n, n ~ (m+1)) => Prependable (MultiSignal n) where
    prepend x (MultiSignal s) = 
        MultiSignal $ liftA2 (+>>) (register x (fmap last s)) s

there are two functions used from CLaSH.Prelude. One is (+>>) :: KnownNat n => a -> Vec n a -> Vec n a and other
last :: Vec (n + 1) a -> a Source

What about Prependable laws, you may ask. Instances of Prependable are like Foldable. Foldable enables function toList.

toList (prep a ax) == a : toList ax

Foldable instance of Signal and MultiSignal hardly has representation in hardware, because it requires iterating whole stream that is infinite. For example, calculating sum as single value of infinitely long stream is not what we can do, but that is what foldr1 (+) express. I am still looking for better way to express Prepenadable and figure out better name.

Isomorphic circuits

Whole idea is that we express circuits using Functor, Applicative and Prependable, than synthesize for both Signal and MultiSignal n domain. We have seen how we can change combinatoric circuits in new domain. In this new domain (for example Signal or MultiSignal) we can use prepend as a function that works as register.

Example of simple circuit is accumulator. This is circuitry that outputs sum of all previously received inputs.

         +-------+
         |       |   +------------+
input ---+  ADD  |   |  prepend   |
         |  (+)  +---+ (register) +----+------ output
      +--+       |   |            |    |
      |  |       |   +------------+    |
      |  +-------+                     |
      +--------------------------------+

And this is how we define such circuit using using new tools.

acc input = output where
    output = prepend 0 (liftA2 (+) input output)

Now we can defer instantiation of such circuitry to the point where we define type signature.

topEntity :: MultiSignal 2 (Signed 6) ->  MultiSignal 2 (Signed 6)
topEntity = acc

                        +----------+
                6 bit   |          |
            ------------+   ADD    |                         
                        | Signed 6 +------------------+             
                   +----+          |                  |     output 
     input         |    |          |                  |   2 * Signed 6         
    2 * Signed 6   |    +----------+                  |    +--------
                   |                                  |    |             
                   +---------------------------+      +----|--------
                        +----------+           |      |    |
                        |          |   +-----+ |      |    |
            ------------+   ADD    |   |     | |      |    |      
                        | Signed 6 +---+ REG +-+-----------+    
                   +----+          |   |6 bit|        |             
                   |    |          |   +-----+        |           
                   |    +----------+                  |
                   |                                  |
                   +----------------------------------+

This is how digital acc circuit is instantiated in MultiSignal 2 (Signed 6). Each wire represent 6 bit bus. At each clock we process two synchronous values.

This looks like free optimization technique, all one need is trade space for speed. Right? Well it is not that easy. As we can see signal needs in worst case propagate trough both adders in single clock cycle to reach register REG. This makes maximal operating frequency approx twice lower compared to circuitry operating in Signal or MultiSignal 1. Improvement can be probably found by exploiting associative properties of addition and is something to look into in future.

mr. Mealy & mr. Moore

Example of mealy :: (s -> i -> (s, o)) -> s -> Signal i -> Signal o as expressed using Prependable.

mealyP f d i = o where
   r = liftA2 f (prepend d s) i
   s = fmap fst r
   o = fmap snd r

Compiler automatically deduce type as

mealyP  :: (Prependable f, Applicative f)
        => (s -> i -> (s, o)) -> s -> f i -> f o

This tells us that we can use mealyP on any type that is Prependable and Applicative. Here we use

We can also in similar terms define moore :: (s -> i -> s) -> (s -> o) -> s -> Signal i -> Signal o

mooreP :: (Prependable f, Applicative f) 
       => (s -> i -> s) -> (s -> o) -> s -> f i -> f o
mooreP fs fo s i = fmap fo r where
     r = liftA2 fs (prepend s r) i

And we can also express fir filter nearly same way as it is on front page of clash-lang.org

fir coeffs x = dotp coeffs (windowP x)
  where
    dotp as bs = sum (zipWith (*) as bs)
    windowP  x = iterateI (prepend def) x

Only difference is that we had to define windowP that works over Prependable instead of Signal. Additionally it requires that MultiSignal is instance of Num. Further details are available in clash-multisignal library.

Conclusion

Using few simple concepts we separate composition and construction of circuits. There is clash-multisignal available and can be used as starting point to play with such structures.

Remote fpga call

Sun, 28 Feb 2016 14:37:00 +0100

Fpga core in CλaSH

Lets make matrix multiplication as Fpga core in language CλaSH. Clash is basically Haskell programming language where Ghc compiler is hacked to generate either verilog, vhdl or system verilog source that can be used by tools (Xilinx Vivado for example) to synthesize digital circuit. Both clash and ghc are free and open sourced.

Multiplication of 2 matrices size 3x3 and using 16 bit arithemtics can be defined as

type M3x3 = Vec 3 (Vec 3  (Signed 16))

matrixMultiply3x3 :: M3x3 -> M3x3 -> M3x3
matrixMultiply3x3 =  fmap ( mulLine (traverse id b)) a
    where 
        mulLine a b = fmap (fold (+) . zipWith (*) b) a

Great. Fpga core! Instead of having instructions run by conventional processor, we have digital circuit that performs multiplication instantly. Time required for copletion depends only on timing for signal propagation trough logic gates.

To test and use this we need to get data in and out of Fpga. This core defines 2 * 3 * 3 * 16 = 288 bits input and 144 bits as output. Wiring all pins directly on output of chip is not an option. Bus infrastructure to get data in and out of fpga is requred.

RedPitaya is already using bus. I am using RedPitaya because it is Fpga board I got. It comes with sources for Fpga. It is running on Xilinx Zynq Soc that has both Fpga and Arm Cortex A9. Arm is running Debian OS and has 512 MB of RAM and Fpga has 28k Logic Cells and 18k LUTs approx.

Lambdaya-bus libraray

Lambdaya-bus library provides both bus core for fpga and client code for communicating with core from application.

On fpga side we need function that takes core as argument and creates bus. We aim for something with this kind of signature.

core2bus :: (Signal a -> Signal b) -> Signal BusIn -> Signal BusOut

That is, we have function that consumes core and provides bus interface. We are close to this, expect ahem, we have to deal with meta programing. The way this to work, compiler must know how large type a and b are and how to divide them in 32 bit chunks.

simpleBus :: Signal BusIn -> Signal BusOut
simpleBus = busBuild $(bTQ matrixMul3x3sig) matrixMul3x3sig

This is how at current state one defines transformation from core to bus. $(bTQ matrixMul3x3sig) is template haskell that works like macro to help deducing proper types as serialization.

It is similar from client side.

From example

multiply :: (M3x3,M3x3) -> NetworkFpgaSetGet M3x3
multiply = callCore $(bTQ matrixMul3x3sig) 5 0 5 0

Magic numbers 5 0 5 0 are page and starting offset for writing and reading from bus. There is some kick start tutrial availabe at github together with presented example.

One can run this same code also directly from Arm without networking overhead. Typeclass FpgaSetGet in this case writes directly on bus.

Porting this library on other Fpga requires implementing FpgaSetGet on client side . There are 4 functions this class is implementing, but only 2 (one set and one get) is required. On Fpga side bus with Signal BusIn -> Signal BusOut is needed.

Fpga bus

Verilog implementation is using extra bits as signals that user must explicitly check to figure out whatever data is available and similar at reading. When there is read request on bus, user must explicitly set bit (either low or high depends on documentation) to indicate that data are written on bus. Haskell enables expressing this in rich type system with same overhead, more expressiveness and less options to make this wrong.

To tell whatever data is available use type Maybe d. That mean that value d (for example data) can be either valid 5 and has value Just 5 or data is not available and value is Nothing.

Our simple bus we are implementing in clash is than

type BusIn = Maybe (FullAddress,ReadWrite,FullDataIn)

Compared to verilog similar interface is provided, except that information about data availability is encoded in type. That means that value can be Nothing or for example Just (0x40500000,Write,0x10). This make reasoning and checking whenever data is available simpler and less error prone. We are unable to not check for data availability because code that does not handle type Maybe (FullAddress,ReadWrite,FullDataIn) will not compile. This approach eliminates kind of errors when mixing up polarity or forgetting about this at all.

It is similar when writing data on bus

type BusOut = Maybe FullDataOut

That is data from core is either valid and is for example Just 42 or is not valid and is Nothing. Working with such type express intent much more clear.

Conclusion

Main pitch for Clash is that it enables developing more ambitious projects. Abstractions Haskell enables might seems scary at first, but one gets feeling about how cores are generated, just like experienced C++ programmer can get grasp of what kind of machine code he can expect. Most if not all of Haskell abstractions come for free in clash and allows describing both intent and circuitry, not just circuitry.

Since haskell is one of few languages having ability to run effectively on both fpga and on pc, we can nicely mix fpga and client side, and I wish that further impovements of lambdaya-bus library will go in further directions to simplify this approach even more. State of lambdaya-bus at this stage with version 0.0.0.2 is just proof of concept as something that can be demonstrated to work.

Functional hardware

Sun, 28 Feb 2016 14:37:00 +0100

Programming FPGA using Haskell

Here is very short introduction to functional programming language Haskel and functional reasoning. For this we will use CλaSH compiler, that is extension of Haskell language being able to convert large set of Haskell code in either VHLD, Verilog or SystemVerilog for now. Installation instructions are available in hackage doc.

If you need just quick peek in examples, there is source code available of all examples presented here and is compiled in VHLD, Verilog and SystemVerilog. Code is automatically generated, but can be used as quick check of what kind of circuit code describes and what to expect from CλaSH compiler.

Premise is that circuits described functional way are considered simpler to reason about, compose and reuse. We are able to describe topology trough functional composition on abstract way without sacrificing about reasoning, how may registries are in use and where logic gates are. This approach allows describing similar if not same circuits as with Verilog and VHDL using new and fresh approach allowing composing more ambitious synchronous digital circuits.

Descriptions is mathematical in way that is trying to use tools from mathematical theory about composition. It is common to see relations described with mathematical laws.

Function application

Before running coding we should explain how calling functions in Haskell works. In most languages if function takes 2 arguments x and y it is called like f(x,y) where equivalent for this in Haskell is f\ x\ y . This come with advantage because Haskell supports partially applied functions where only one out of two arguments is applied. Lets say that signature of f is Int -> Int -> Bool. We can interpret this as - it takes two integers x an y and it returns boolean. When only first argument x is applied it returns function whit hremaining signature. When applying on function Int -> Int -> Bool first Int remaining is Int -> Bool. That is function that takes Int and it returns Bool.

-- function of 2 Int, that telse if 
-- 1st argument is greater then 2nd
greater :: Int -> Int -> Bool 
greater x y = x > y

-- takes y and tels whatever it is greater than 2 
isgt2 :: Int -> Bool 
isgt2 y = greater 2 y

or less verbose as partially applied

isgt2 :: Int -> Bool
isgt2 = greater 2

One way to think about functions in Haskell is that each function takes only one argument and it returns one value that can be function. Signature of greater can be seen as greater :: Int -> ( Int -> Bool ). So it takes an Int and it returns function Int -> Bool. That is function that takes Int and returns Bool.

In Haskell every function returns something. Pure functions, does not execute any action, but just transform input data and return relevant result. Pure functions, has important property that they always returns same output for same input and so they don’t have access to some external time changing data or internal state. In Haskell there is strong force to separate effects from pure functions.

Function composition

Functional programming is about composition. Here it is example of signatures of 2 functions.

funcA2B :: a -> b
funcB2C :: b -> c

funcA2B is function that takes type a and returns b, one example is that it takes Int and returns Bool.funcB2C takes b and it returns c. For example it takes Bool and returns Bool. Having this we are able to create function

funcA2C :: a -> c

by composing together funcA2B and funcB2C to get funcA2C.

For composing two functions we need function

composeFunc :: (b->c) -> (a->b) -> a -> c
composeFunc f g x = f (g x)

First we apply x on g and then we apply result on f.
Moving back to composeFunc it takes 3 arguments. First two are functions, f with signature b->c and g with signature a->b, 3rd param x is of type a. Function returns type c and is same type that f returns. Looking differently it takes two functions that is b->c and a->b and it returns function a -> c.

For example

minus1 x = x - 1
largeNum x = x > 3

superLargeNum = composeFunc largeNum minus1

superLargeNum is function composed by largeNum and minus1.Type of each function is well defined, but we can either define it manually or compiler can automatically deduce it.

-- simplified types
minus1 :: a -> a
largeNum :: a -> Bool
superLargeNum :: a -> Bool 

-- actual types
minus1 :: Num a => a -> a
largeNum :: (Num a, Ord a) => a -> Bool
superLargeNum :: (Num a, Ord a) => a -> Bool

We can read this, that function superLargeNum transforms type a into Bool. Type a has to be defined for class Num and Ord. Num is class that has defined function (-) as minus operator. (among others) and class Ord has defined (>).

composeFunc is commonly used and in Haskell it is defined as operator (.).

(.) = composeFunc

Using this, one can alternatively define superLargeNum as

superLargeNum = largeNum . minus1
-- or 
superLargeNum = (> 3) . (- 1) 
-- or
superLargeNum x = (x - 1) > 3

Operator . comes from function composition as defined in mathematics f ∘ g . Here we have showed implemention of . as in composeFunc, but sometimes instead of implementation we get only laws. For function (.) holds.

If id is identity function that returns argument

id :: a -> a
id x = x

then function composition laws for ∘ are

id . f == f . id == f
f . g . h == (f . g) . h == f . (g . h)

Instead of having function implementation available we sometimes have available laws that function obeys. It helps reasoning about how function behaves without knowing what it does. Laws also goes hand to hand with implementation.

Functor

Lets take for example type in CλaSH called Signal a. This represent type a changing with clock. Signal is concrete example of functor and a is type embedded in Signal.

Other than function composition of Signal a there is different composition available for functor.

funcA2B :: a -> b
signalA :: Signal a

If we have function of type a -> b and Signal a, than functor enables us to get Signal b

fmap :: (a -> b) -> Signal a -> Signal b

Functor obeys two laws

fmap id == id
fmap (p . q) == (fmap p) . (fmap q)

Or equivalently when applying signal.

fmap id signal == signal
fmap (p . q) signal == fmap p (fmap q signal)

Knowing this we can aswer next question. Does fmap over Signal uses any registries as for example D flip-flop?

Answer is, if that would be case, neither of laws would hold. Form first law it would imply that on left we have signal delayed by 1 clock, and on right non delayed signal and they are not same. Second law would imply delay by 1 clock on left where right side made 2 delays, each by one fmap calls.

To generate core we define function topEntity. Generic type a should be concrete and in this case we will use Signed 7 what is 7 bit signed integer.

topEntity :: Signal (Signed 7) -> Signal Bool
topEntity signal = fmap superLargeNum signal 

Executing command fmap can be used as operator. That is <$>. Alternatively we can implement topEntity also as

topEntity signal = superLargeNum <$> signal
-- or point free version
topEntity = fmap superLargeNum
-- or using fmap as operator
topEntity = superLargeNum `fmap` signal

It is hard to tell witch version is most common among haskellers, but we can be sure, that due to laws all of them behaves same.

Compiling this exact into Verilog generates code as expected.

Mealy machinery

For generating output based on previous stored value we can use mealy function. Lets implement integrator using mealy machine. With integrator we have in mind function that takes Signal a and produces Signal a and is representing sum of all previous values including current.

integrator signal = mealy mf 0 signal
    where 
        mf state input = (nextstate,output)
            where
                nextstate = state + input
                output = nextstate

mealy is function that takes 3 arguments. First parameter is a function on how to generate next state from state and signal value. Signature of this function is s -> i -> (s,o). In our code that is function called mf. mf is defined in where block for local visibility so can not be used out of
integrator . What this mf function does it takes 2 arguments state and input and it returns tuple (nextstate,output). Next clock cycle nextstate will be passed again in mf as argument state. 2nd argument of integrator 0 is initial state value. Generated core will provide reset signal that sets state to initial value.

If we now need to create FPGA core, we need to provide topEntity. Here it is full source instantiated with Fixed point arithmetics. We arbitrarily choose SFixed 2 8, This is 10 bit signed fixed point number. It is representing rational numbers from -2 <= x < 2.

module Integrator where
import CLaSH.Prelude

integrator signal = mealy mf 0 signal
    where 
        mf state input = (nextstate,output)
            where
                nextstate = state + input
                output = nextstate

topEntity :: Signal (SFixed 2 8) -> Signal (SFixed 2 8)
topEntity = integrator

integrator can be used in other modules, to build larger and more ambitious circuits. For example to make integrator of integrated signal so that output of first integrator is feed in second one.

intInt = integrator . integrator

Vector

Vec is sized vector with compile type defined size holding elements of same type. It is similar to tuple, except that all elements are of same type.

Vec 5 (Signed 7) is type that holds 5 elements of type Signed 7 what is 7 bit signed number. Vec is also an functor.

For example

vs :: Vec 6 (Signed 9)
vs = 1 :> 2 :> 3 :> 4 :> 5 :> 6 :> Nil

vb :: Vec 6 Bool
vb = fmap (> 3) vs  -- that is <False,False,False,True,True,True>

Operator :> is right-associativity operator that prepends vector on right with value on left. Nil is empty vector and is used, because :> expects vector on right side.

Size of Vec is defined at compile time and can be generic. Lets take look on one of many functions from Vec libraray that is replicate and has prototype

replicate :: SNat n -> a -> Vec n a
-- "replicate n a" returns a vector that has `n` copies of `a`.

Vec 5 a is not same as Vec 6 a and it means that replicate returns different type based on argument n. For this to work, n is of type SNat x and is different type for each x. Value that has type Signed 5 as 5 bit signed value can be -2 or 7, where value d3 that has type SNat 3 represents number 3 as unique type.

Moving average

Moving average is simple low pass FIR filter expressed as sum of last n values. We will deliberately skip division in our example, so we will in reality talk about moving sum.

Here is straight forward and naive option to describe moving average using mealy.

movingAvarage n signal = mealy mf (replicate n 0) signal
    where
        mf state input = (nexts,output)
            where 
                nexts = input :> init state
                output = fold (+) nexts

First argument n is number of accumulated value is also size of Vec used as internal state storage. Type of internal state is deduced as Vec n a and is deduced from type of initial state value replicate n 0 that returns Vec that returns n copies of 0.

init :: Vec (n + 1) a -> Vec n a is function that takes Vec with size n+1 and returns all except last element that is Vec of size n.

nexts expressed as next state is vector right shifted by previous value and perpended :> with current clock input value. Operation works as fifo shift register.

fold is function best expressed with same picture as in manuals

From signature we can conclude that fold :: (a -> a -> a) -> Vec (n + 1) a -> a takes 2 arguments. First is function of type (a -> a -> a) an second argument is of type Vec (n + 1) a. Function is than applied over vector in tree like structure, enabling minimum latency.

Function f from out case is function (+) (in haskell operator in brakets is used as function). and has prototype a -> a -> a and is applied over state.

There is better

Lets try some optimization of moving average from previous section. Observing totals we can conclude we don’t need that many adders. Total output is changed at each clock only by value that enters fifo from one side and value that pops out of fifo on other. At each clock we need to subtract value that pops out and add value that enters from total. This comes at expanse of 2 extra sized registers (previous solution can be reduced by 1 sized register) but requires only 2 sized adders.

movingAvarage2 n signal = mealy mf ((replicate n 0),0) signal
    where
        mf (vec,total) input = ((nextVec,nextTot),output)
            where 
                output = total + input - (last vec)
                nextVec = input :> init vec
                nextTot = output

mf has at this point signature (Vec n a,a) -> a -> ((Vec n a,a),a). Internal state type is tuple where first value is vec used as fifo and total accumulated in fifp.vecandtotalare unpacked from tuple in input argument, so we are able to access this value, without unpacking them in body. Equivalent, but more verbosemf` implemetaion is sketched as

mf state input = ...
    where 
        vec = fst state -- first element of tuple
        total = snd state -- second element of tuple
        output = ...

Circuit composition

Great power of composition comes from separating logic into reusable parts and then composing them together in larger blocks. Function (.) and fold are good examples we have used so far. Now lets try something similar, by designing feedback loop.

          +---+    +---+
input -->-| f |-->-| g |-->-+-->-- output 
          +---+    +---+    |
            |               ∨
            ∧      +---+    |
            +----<-| h |-<--+
                   +---+     

First lets figure out prototypes of each function f, g and h.

f :: Signal a -> Signal b -> Signal c
g :: Signal c -> Signal d
h :: Signal d -> Signal b

and feedback loop can be written directly from circuit diagram as

feedbackLoop :: (Signal a -> Signal b -> Signal c) 
                -> (Signal c -> Signal d)
                -> (Signal d -> Signal b)
                -> Signal a 
                -> Signal d
feedbackLoop f g h input = out where
    out = g fout
    fout = f input (h out)

If user has available functions that works over primitive values like Signed instead Signal (Signed 16) for example, he can use fold. For example if

g :: Signed 16 -> Signed 16

Then gs working over signal would be constructed from g

gs :: Signal (Signed 16) -> Signal (Signed 16) 
gs = fmap g
-- or more verbose
gs sig = fmap g sig

For function over 2 input arguments we can use library function liftA2

liftA2 :: (a -> b -> c) -> functor a -> functor b -> functor c

Where functor is in our example Signal For example to get function minus (-) to operate over Signal we need to apply liftA2.

signalMinus :: Signal a -> Signal a -> Signal a
signalMinus = liftA2 (-)

To construct negative feedback looking like

                   +---+
input -->-( - )-->-| g |-->-+-->-- output 
            |      +---+    |
            ∧               ∨ 
            +--------<------+

Using feedbackLoop,

negativeFeedback :: Num a => 
                    (Signal a -> Signal a) -> 
                    Signal a ->
                    Signal a
negativeFeedback g = feedbackLoop (liftA2 (-)) g id

We have replaced h by id and f argument is liftA2 (-)

There is subtle issue with this and in some cases this circuit can not be synthesized. That is because we have feedback loop, so we have made sure that there is delay in g function. If g function is for example id or fmap id so it works like wire this circuit is not stable any more. To overcome this, we have to introduce delay in feedback. Function h from previous diagram, becomes register 0 instead of id. function

negativeFeedback :: Num a => (Signal a -> Signal a) -> Signal a -> Signal a
negativeFeedback g = feedbackLoop (liftA2 (-)) g (register 0)

register :: a -> Signal a -> Signal a is a function, that takes inital value, that outputs this value before remaining of stream. register is available in CλaSH libraray, but can be implemented using mealy as

register initialValue signal = mealy mf initialValue 
    where 
        mf prevS input = (input,prevS)

What is even more surprising is that it can be done even vice versa. That is mealey can be expressed in terms of register. For details check examples on github

Conclusion

There are lot of features that were no covered. But are invaluable during development

repl, (read eval print loop) that allows interactive development, type deduction
ability to simulate in repl or compile in CPU native executable
testebenches that generates VHDL / Verilog / Systemverilog and can be used directly in IDE
full featured library, (ram and rom access and initalisation, multiple clock domains, type safe delays … )

From my and experience of many it takes lot of time and practice to grasp new programming language, what Haskell for those not familiar with functional programming certainly is. Reader with interest will be able to find lot of free resources available online for all levels of experience with open and active community.

Generic C

Thu, 08 Jan 2015 14:37:00 +0100

Common way to write generic functions in C is to use macros. Problem with macros is that that they are hard to read, and hard to support. Just take max for example and it gets worse in this terms when complex functions are required. sglib is another example. This code just does not feel C any more.

Approach in generic max without macros is:

//use max with integers
typedef int generic_max_t;

//this inserts static max() 
//that accepts generic_max_t as type
#include "max_generic.h"  

main(){
  int a=1;
  int b=2;
  int m = max(a,b);
  printf("%i",m);
}

and this is implementation of “max_generic.h”

static generic_max_t max(generic_max_t a, generic_max_t b){
  if(a>=b)
    return a;
  else
    return b;
}

Generic functions are implemeted with generic type. In this example generic_max_t was used. Type is first instatiated with typedef int generic_max_t; and after that generic code in injected using #include directive that works like copy-paste. For this to work, all generic functions should be declared as static.

Advantage of such code is that is pure C without funny macros. Code is reusable with different types, but unfortunatly only once in each translation unit.

Here is another example of generic ring buffer with non trivial type to store.

//usage example
#include <stdio.h>


typedef struct {
    double x;
    double y;
    double z;
}point_t;

//we want point_t to be element of our circular buffer
typedef point_t circular_element_t;

//at this point we inject static code that accepts circular_element_t as type
#include "circular.generic.c"  

circular_element_t buffer_space[20];

circular_buffer_t circular_buffer = {
  .buffer = buffer_space,
  .length = sizeof(buffer_space)/sizeof(buffer_space[0]),
};

int main(){
  generic_curcular_buffer_init(&circular_buffer);
  point_t p = {1,2,3};
  generic_curcular_buffer_push(&circular_buffer,&p);
  p.x=p.y=p.z=0;
  generic_curcular_buffer_pop(&circular_buffer,&p);  
  printf("%f %f %f",p.x,p.y,p.z);
  return 0;
}

and implementation

// file: circular.generic.c
// generic ring buffer
//
// extrnaly defined type is 
// circular_element_t;

typedef struct{
  circular_element_t * buffer;
  int length;  
  int push;
  int pop;  
} circular_buffer_t;
static void generic_curcular_buffer_init(circular_buffer_t * cb){
  cb->push = 0;
  cb->pop = 0;
}
//return 0 or sucess or -1 on error
static 
int generic_curcular_buffer_push(circular_buffer_t * cb, 
                                 const circular_element_t* element)
{
  int push = cb->push+1;
  if(push == cb->length) {
    push  = 0;
  }
  if(push == cb->pop){
    return -1; //full
  }
  cb->buffer[cb->push] = *element;
  cb->push = push;
  return 0;
}
//return 0 or sucess or -1 if empty
static
int generic_curcular_buffer_pop(circular_buffer_t * cb, 
                                circular_element_t* element)
{
  if( cb->pop ==  cb->push) {
    return -1; //empty
  }
  int pop = cb->pop+1;
  if(pop == cb->length){
    pop=0;
  }
  *element = cb->buffer[cb->pop];
  cb->pop = pop;
  return 0;
}

Another example whith reuse of generic code, is availabe on github

Memoization in C++

Sun, 21 Sep 2014 22:49:53 +0200

Memoization is very useful technique for developing algorithms. Python3 has native support for memoization and here is how it is used.

from functools import lru_cache

@lru_cache #memoization
def fib(n):
    if n < 2:
        return 1
    else:
        return fib(n-1) + fib(n-2)

Similar feature can be implemeted in c++ . Here is an example on how to use.

MEMOIZATION(uint64_t, fib,(int n))
{
   if(n < 2)
      return 1;
   return fib(n-1)+fib(n-2);
}

originaly defined uint64_t fib(int n) has to be wrapped in macro that takes 3 parameters. return_type, func_name and arguments. so it becomes MEMOIZATION(uint64_t, fib,(int n)) From user’s perspective it looks similar to python’s version.

Here is full implementation of macro MEMOIZATION, Memo class and helper function. This implementation is not same as lru_cache where old items in cache are discarded once limit is reached.

#include  <map>
#include  <tuple>

#define MEMOIZATION(ret,name,params) \
  ret name##nonmemo params; \
  auto name = memo_wrapper(name##nonmemo);\
  ret name##nonmemo params

template<class...Arg> struct Memo;

template<class R, class...Arg>
struct Memo<R(*)(Arg...)>
{    
    using funcpoint_t =  R(*)(Arg...a);
    using tuple_t= std::tuple<Arg...>;
    using map_t = std::map<tuple_t,R>;
    
    Memo(funcpoint_t fp):mFp(fp){}
    
    const R&  operator()(Arg...arg)
    {
       tuple_t tup(arg...);
       auto it = mMap.find(tup);
       if(it != mMap.end())
          return it->second;
       else
          return mMap.insert(std::make_pair(tup,mFp(arg...))).first->second;
    }
    
    private:
    funcpoint_t mFp;
    map_t mMap;
};

template <class R, class...Arg>
Memo< R(*)(Arg...)> 
memo_wrapper( R(*f)(Arg...)  ) 
{
    return Memo< R(*)(Arg...)>(f);
}

technobable

Solving Steve Ballmer's Interview Riddle with Game Theory

The quest

Take a deep breath

A Simpler Problem

Steve as the honest randomizer

Steve as the tricky adversary

Solving with Linear Programming

From Game Tree to Game Graph

Symmetries

Result

Further Reading

Automatc frequency domain analysis of digital ciruits

Main Idea

Example of use

Details

acyclic circuits

cyclic circuits

What next

Isomorphism of digital circuits

Whole idea summary

Functor

Functor for MultiSignal

Applicative

MultiSignal as applicative functor

Prependable

Isomorphic circuits

mr. Mealy & mr. Moore

Conclusion

Remote fpga call

Fpga core in CλaSH

Lambdaya-bus libraray

Fpga bus

Conclusion

Functional hardware

Programming FPGA using Haskell

Function application

Function composition

Functor

Mealy machinery

Vector

Moving average

There is better

Circuit composition

Conclusion

Generic C

Memoization in C++